1. Field of the Invention
The present invention relates to a method and an apparatus for supporting verification in large-scale integration (LSI) design.
2. Description of the Related Art
In LSI design, improvement in work efficiency by shortening a design period has conventionally been demanded. However, in the LSI design, a verification process, which is rather time consuming, to verify whether an LSI properly operates is essential. Especially for an LSI that is required to be large-scale, to have high performance, to be high-speed, and to be low-power consuming, the verification process is important to maintain high quality.
The verification process includes a timing verification. In the timing verification, synopsys design constraint (SDC) is widely used as a file format for condition data for various settings in a timing verification tool. For a setting condition file for operation in a system (user) mode in the SDC, it is possible for a circuit designer to create the setting condition file according to circuit specifications.
On the other hand, for a setting condition file for a test mode operation in the SDC, unless a person conducting test synthesis understands details of test synthesis by the circuit designer, it is difficult for the person to create the setting condition data. Therefore, the setting condition file for the test mode operation has conventionally been created by adding or rewriting a clock domain, an external pin name, a test pin name, and various timing values based on a common template provided for each testing scheme. Related conventional technologies are disclosed in, for example, Japanese Patent Laid-Open Publication Nos. 2000-222452, 2000-276515, and 2000-348086.
However, because the setting condition file for the test mode operation is manually created by a user, an error is likely to occur, and wrong information can be included in the setting condition file.
In the conventional technologies described above, clocks in the system mode operation and in the test mode operation are never contrasted with each other. Consequently, even when the setting condition file for operation in the system mode includes setting condition data that is partially effective in the test mode, such setting condition data is also included in the setting condition file for the test mode operation. When such setting conditions file for the test mode operation is used in the timing verification tool, unnecessary verification is performed. As a result, a verification period becomes long.
Furthermore, timing set in the template does not always correspond with timing set in an automatic test pattern generation (ATPG) tool. As a result, pattern verification using the ATPG tool and timing verification using the timing verification tool do not correspond with each other. Consequently, an error can occur and such a designing process is required to be repeated for correction. Moreover, in creating the setting condition file for the test mode operation, number of processes required for creation is extremely large. This increases a load on the user.